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MC14066B Quad Analog Switch/Quad Multiplexer
The MC14066B consists of four independent switches capable of controlling either digital or analog signals. This quad bilateral switch is useful in signal gating, chopper, modulator, demodulator and CMOS logic implementation. The MC14066B is designed to be pin-for-pin compatible with the MC14016B, but has much lower ON resistance. Input voltage swings as large as the full supply voltage can be controlled via each independent control input.
Features http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 P SUFFIX CASE 646 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G 1 14 SOEIAJ-14 F SUFFIX CASE 965 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) MC14066B ALYWG 14 066B ALYWG G 14066BG AWLYWW MC14066BCP AWLYYWWG
* * * * * * *
Triple Diode Protection on All Control Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise - 12 nV/Cycle, f 1.0 kHz typical Pin-for-Pin Replacement for CD4016, CD4016, MC14016B For Lower RON, Use The HC4066 High-Speed CMOS Device Pb-Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin ISW PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Control Pin Switch Through Current Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 25 500 -55 to +125 -65 to +150 260 Unit V V mA mA mW C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 7
1
Publication Order Number: MC14066B/D
MC14066B
PIN ASSIGNMENT
IN 1 OUT 1 OUT 2 IN 2 CONTROL 2 CONTROL 3 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD CONTROL 1 CONTROL 4 IN 4 OUT 4 OUT 3 IN 3
BLOCK DIAGRAM
CONTROL 1 IN 1 CONTROL 2 IN 2 CONTROL 3 IN 3 CONTROL 4 IN 4 13 2 1 5 3 4 6 9 8 12 10 11 OUT 4 VDD = PIN 14 VSS = PIN 7 OUT 3 OUT 2 OUT 1
LOGIC DIAGRAM AND TRUTH TABLE (1/4 OF DEVICE SHOWN)
IN/OUT CONTROL
Control 0 = VSS 1 = VDD Switch OFF ON Logic Diagram Restrictions VSS Vin VDD VSS Vout VDD
OUT/IN
CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN)
VDD
VDD VDD
VSS VDD CMOS INPUT
VDD
VDD
VDD
300 W VSS VSS
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SWITCHES IN AND OUT (Voltages Referenced to VSS) CONTROL INPUTS (Voltages Referenced to VSS) SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
2. Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance. 3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)
ELECTRICAL CHARACTERISTICS
Capacitance, Feedthrough (Switch Off)
Capacitance, Switch I/O
Off-Channel Leakage Current (Figure 6)
DON Resistance Between Any Two Channels in the Same Package
ON Resistance
Output Offset Voltage
Recommended Static or Dynamic Voltage Across the Switch (3) (Figure 1)
Recommended Peak-to- Peak Voltage Into or Out of the Switch
Input Capacitance
Input Leakage Current
High-Level Input Voltage
Low-Level Input Voltage
Total Supply Current (Dynamic Plus Quiescent, Per Package
Quiescent Current Per Package
Power Supply Voltage Range
Characteristic
DVswitch
Symbol
ID(AV)
DRon
VOO
VDD
CI/O
CI/O
VI/O
Ron
VIH
IDD
Cin
VIL
Ioff
Iin
VDD
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
15
--
- -
-
-
-IIIIIII Channel On
-
-
Control Inputs: Vin = VSS or VDD, Switch I/O: VSS v VI/O v VDD, and DVswitch v 500 mV (3)
Switch Off
Vin = VIL or VIH (Control) Channel to Channel or Any One Channel
DVswitch v 500 mV Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch)
Vin = 0 V, No Load
Channel On or Off
Vin = 0 or VDD
Ron = per spec, Ioff = per spec
Ron = per spec, Ioff = per spec
TA = 25_C only The channel component, (Vin - Vout)/Ron, is not included.)
Test Conditions
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MC14066B
(3),
3 Min 3.5 7.0 11 3.0 - - - - - - - - - - 0 0 - - - - - - - - - 55_C Typical 0.1 100 0.25 0.5 1.0 Max VDD 800 400 220 600 1.5 3.0 4.0 70 50 45 18 - - - - - - - Min 3.5 7.0 11 3.0 - - - - - - - - - - 0 0 - - - - - - - - (0.07 mA/kHz) f + IDD (0.20 mA/kHz) f + IDD (0.36 mA/kHz) f + IDD 0.00001 Typ (2) 0.05 0.005 0.010 0.015 25_C 0.47 2.75 5.50 8.25 2.25 4.50 6.75 250 120 80 5.0 10 25 10 10 10 - - - 0.1 100 1050 500 280 0.25 0.5 1.0 MaxIII Min Max VDD 600III 0 300 7.5 1.5 3.0 4.0 15 70 50 45 18 - - - - - 3.5 7.0 11 3.0 - - - - - - - - - - 0 - - - - - - - - 125_C 1000 1.0 1200 520 300 VDD 135 95 65 1.5 3.0 4.0 7.5 15 30 18 - - - - - - - Vp-p Unit mV nA mV mA mA mA pF pF pF W W V V V
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII I IIII I I I I IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIII IIII IIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII IIII IIIIIIIIIIIIIIII IIIIII IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I IIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIII IIII IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII
4. The formulas given are for the typical characteristics only at 25_C. 5. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25_C unless otherwise noted.)
Crosstalk, Control Input to Signal Output (Figure 5) VSS = - 5 Vdc (R1 = 1 kW, RL = 10 kW, Control tTLH = tTHL = 20 ns)
Channel Separation (Figure 4) (Vin = 5 Vp-p, RL = 1 kW, fin = 8.0 MHz) (Switch A ON, Switch B OFF)
Feedthrough Attenuation (Switch OFF) VSS = - 5 Vdc (Vin = 5 Vp-p, RL = 1 kW, fin = 1.0 MHz) (Figure 3)
Bandwidth (Switch ON) (Figure 3) VSS = - 5 Vdc (RL = 1 kW, 20 Log (Vout/Vin) = - 3 dB, CL = 50 pF, Vin = 5 Vp-p)
Second Harmonic Distortion VSS = - 5 Vdc (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, RL = 10 kW, f = 1.0 kHz)
Propagation Delay Times Input to Output (RL = 10 kW) tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns
Control to Output (RL = 1 kW) (Figure 2) Output "1" to High Impedance
High Impedance to Output "0"
High Impedance to Output "1"
Output "0" to High Impedance
Characteristic
VSS = - 5 Vdc
VSS = 0 Vdc
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MC14066B
tPLH, tPHL
Symbol
4 tPZH tPHZ tPZL tPLZ - - - - - VDD Vdc 5.0 5.0 5.0 5.0 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min - - - - - - - - - - - - - - - - - - - - Typ (5) - 50 - 50 300 0.1 20 10 7.0 65 60 20 15 60 20 15 40 35 30 40 35 30 Max 120 40 30 120 40 30 80 70 60 80 70 60 40 20 15 - - - - - mVp-p MHz Unit dB dB ns ns ns ns ns %
MC14066B
ORDERING INFORMATION
Device MC14066BCP MC14066BCPG MC14066BD MC14066BDG MC14066BDR2 MC14066BDR2G MC14066BDTR2 MC14066BDTR2G MC14066BF MC14066BFG MC14066BFEL MC14066BFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 / Tape & Reel 50 Units / Rail 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC14066B
TEST CIRCUITS
Vout VC ON SWITCH CONTROL SECTION OF IC LOAD V 20 ns VC tPZH Vout Vout 10% 90% Vin 90% 50% 10% RL Vx VDD CL
VSS tPHZ 90% tPLZ
tPZL
Vin = VDD Vx = VSS Vin = VSS Vx = VDD
SOURCE
10%
Figure 1. DV Across Switch
Figure 2. Turn-On Delay Time Test Circuit and Waveforms
VC = VDD FOR BANDWIDTH TEST VC = VSS FOR FEEDTHROUGH TEST VDD - VSS 2 Vin RL VC VDD VSS CL Vout
VDD - VSS 2 Vin VDD RL CL
VSS
RL
CL
Figure 3. Bandwidth and Feedthrough Attenuation
Figure 4. Channel Separation
OFF CHANNEL UNDER TEST Vin 1k RL 10 k VC = -5.0 V TO +5.0 V SWING Vout CL = 50 pF A CONTROL SECTION OF IC VDD VSS
VSS VDD
Figure 5. Crosstalk, Control to Output
Figure 6. Off Channel Leakage
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MC14066B
VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k VDD VSS 1 kW RANGE X-Y PLOTTER
Figure 7. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS
350 R ON , ON" RESISTANCE (OHMS) R ON , ON" RESISTANCE (OHMS) 300 250 200 150 100 50 0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 TA = 125C 25C -55 C 350 300 250 200 150 100 50 0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 TA = 125C 25C -55 C
8.0
10
6.0
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 8. VDD = 7.5 V, VSS = - 7.5 V
Figure 9. VDD = 5.0 V, VSS = - 5.0 V
700 RON , ON" RESISTANCE (OHMS) RON , ON" RESISTANCE (OHMS) 600 500 400 300 200 100 0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2
350 300 250 200 150 100 50 0 -10
TA = 25C
VDD = 2.5 V
TA = 125C 25C -55 C 4.0 6.0 8.0 10
5.0 V 7.5 V
-8.0 -6.0 -4.0 -2.0
0
0.2
4.0
6.0
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 10. VDD = 2.5 V, VSS = - 2.5 V
Figure 11. Comparison at 25C, VDD = - VSS
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MC14066B
APPLICATIONS INFORMATION Figure A illustrates use of the Analog Switch. The 0-to-5 V digital control signal is used to directly control a 5 V peak-to-peak analog signal. The digital control logic levels are determined by V DD and VSS. The VDD voltage is the logic high voltage, the VSS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VSS. The analog voltage must not swing higher than V DD or lower than V SS. The example shows a 5 V peak-to-peak signal which allows no margin at either peak. If voltage transients above
+5 V VDD VSS +5.0 V 5 Vp-p ANALOG SIGNAL +5 V SWITCH IN
V DD and/or below V SS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and V SS is 18 V. Most parameters are specified up to 15 V which is the recommended maximum difference between V DD and V SS.
SWITCH OUT
5 Vp-p ANALOG SIGNAL
+ 2.5 V
GND EXTERNAL CMOS DIGITAL CIRCUITRY 0-TO-5 V DIGITAL CONTROL SIGNALS MC14066B
Figure A. Application Example
VDD DX SWITCH IN DX VSS SWITCH OUT
VDD DX
DX VSS
Figure B. External Germanium or Schottky Clipping Diodes
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MC14066B
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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MC14066B
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC14066B
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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11
EEE CCC EEE CCC
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC14066B
PACKAGE DIMENSIONS
SOEIAJ-14 CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14066B/D

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